IPACK2009-89055  

Development of a New Wire Bonding Technology on Integrated Circuit Devices

IPACK2009-89163  

COPPER PLATING PROCESS FOR THROUGH SILICON VIA WITH HIGH ASPECT RATIO IN ADVANCED PACKAGING

IPACK2009-89245  

Stress Measurement Errors in Flip Chip Packages Using Multi-Element Sensor Rosettes on (111) Silicon

IPACK2009-89247  

Experimental study of the high cycle fatigue of thin film metal on Polyethylene Terephthalate for flexible electronics applications

IPACK2009-89274  

High-Density Room-Temperature 3D Chip-Stacking Using Mechanical Caulking with Compliant Bump and Through-Hole-Electrode

IPACK2009-89304  

CHARACTERIZING AND MINIMIZING VOIDS IN QUAD FLAT NO-LEAD (QFN) DEVICE ASSEMBLY USING PB-FREE SOLDER ALLOYS

IPACK2009-89336  

Flat Tree Networks

IPACK2009-89355  

Integrating Novel Packaging Technologies for Large Scale Computer Systems

IPACK2009-89380  

Effects of TSV (Through Silicon Via) Interposer/Chip on the Thermal Performances of 3D IC Packaging

IPACK2009-89414  

INVESTIGATION OF TRANSFER MOLD PROCESS EFFECTS ON SEMICONDUCTOR PACKAGE WARPAGE